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March 1996
NDC7001C Dual N & P-Channel Enhancement Mode Field Effect Transistor
General Description
These dual N and P-channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process has been designed to minimize on-state resistance, provide rugged and reliable performance and fast switching. These devices is particularly suited for low voltage, low current, switching, and power supply applications.
Features
N-Channel 0.51A, 50V, RDS(ON) = 2 @ VGS=10V P-Channel -0.34A, -50V. RDS(ON)= 5 @ VGS=-10V. High density cell design for low RDS(ON). Proprietary SuperSOTTM-6 package design using copper lead frame for superior thermal and electrical capabilities. High saturation current.
____________________________________________________________________________________________
4
3
5
2
6
SuperSOTTM-6
1
Absolute Maximum Ratings
Symbol VDSS VGSS ID Parameter Drain-Source Voltage
T A = 25C unless otherwise noted
N-Channel 50 20
(Note 1a)
P-Channel -50 -20 -0.34 -1 0.96 0.9 0.7 -55 to 150
Units V V A
Gate-Source Voltage - Continuous Drain Current - Continuous - Pulsed
0.51 1.5
PD
Maximum Power Dissipation
(Note 1a) (Note 1b) (Note 1c)
W
TJ,TSTG
Operating and Storage Temperature Range
C
THERMAL CHARACTERISTICS RJA RJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case
(Note 1a) (Note 1)
130 60
C/W C/W
(c) 1997 Fairchild Semiconductor Corporation
NDC7001C.SAM
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Symbol Parameter Conditions Type Min Typ Max Units OFF CHARACTERISTICS BVDSS IDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 A VGS = 0 V, ID = -250 A Zero Gate Voltage Drain Current VDS = 40 V, VGS = 0 V TJ = 125C VDS = -40 V, VGS = 0 V TJ = 125C IGSSF IGSSR VGS(th) Gate - Body Leakage, Forward Gate - Body Leakage, Reverse VGS = 20 V, VDS = 0 V VGS = -20 V, VDS= 0 V VDS = VGS, ID = 250 A TJ = 125C VDS = VGS, ID = -250 .A TJ = 125C RDS(ON) Static Drain-Source On-Resistance VGS = 10 V, ID = 0.51 A TJ = 125C VGS = 4.5 V, ID = 0.35 A VGS = -10 V, ID = -0.34 A TJ = 125C VGS = -4.5 V, ID = -0.25 A ID(on) gFS On-State Drain Current VGS = 10 V, VDS = 10 V VGS = -10 V, VDS = -10 V Forward Transconductance VDS = 10 V, ID = 0.51 A VDS = -10 V, ID = -0.34 A DYNAMIC CHARACTERISTICS N-Ch P-Ch N-Ch P-Ch 1.5 -1 400 250 mS P-Ch N-Ch P-Ch All All P-Ch N-Ch P-Ch N-Ch 50 -50 1 500 -1 -500 100 -100 nA nA A V
ON CHARACTERISTICS (Note 2) Gate Threshold Voltage N-Ch 1 0.8 -1 -0.8 1.9 1.5 -2.5 -2.2 1 1.7 1.6 2.5 4 5.3 2.5 2.2 -3.5 -3 2 3.5 4 5 10 7.5 A V
Ciss Coss Crss
Input Capacitance
N-Channel VDS = 25 V, VGS = 0 V, f = 1.0 MHz P-Channel VDS = -25 V, VGS = 0 V, f = 1.0 MHz
N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch
20 40 13 13 5 4
pF
Output Capacitance Reverse Transfer Capacitance
pF pF
NDC7001C.SAM
Electrical Characteristics (TA = 25oC unless otherwise noted)
Symbol Parameters Conditions Type Min Typ Max Units SWITCHING CHARACTERISTICS (Note 2) tD(on) Turn - On Delay Time Turn - On Rise Time N-Channel VDD = 25 V, ID = 0.25 A, VGS = 10 V, RGEN = 25 P-Channel VDD = -25 V, ID = -0.25 A, VGS = -10 V, RGEN = 25 N-Ch P-Ch N-Ch P-Ch tD(off) Turn - Off Delay Time N-Ch P-Ch N-Ch P-Ch Qg Qgs Qgd Total Gate Charge Gate-Source Charge N-Channel VDS = 25 V, ID = 0.51 A, VGS = 10 V P-Channel VDS = -25 V, ID = -0.34 A, VGS = -10 V N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch DRAIN-SOURCE DIODE CHARACTERISTICS IS ISM VSD Maximum Continuous Source Current N-Ch P-Ch Maximum Pulse Source Current (Note 2) Drain-Source Diode Forward Voltage N-Ch P-Ch VGS = 0 V, IS = 0.51 A (Note 2) VGS = 0 V, IS = -0.34 A (Note 2)
Notes: 1. RJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RJC is guaranteed by design while RCA is determined by the user's board design.
6 14 6 6 11 13 5 6 1 1.3 0.19 0.23 0.33 0.38
20 20 20 20 20 20 20 20
nS
tr
tf
Turn - Off Fall Time
nC nC
Gate-Drain Charge
nC
0.51 -0.34 1.5 -1 0.8 -0.8 1.2 -1.2
A
A V
N-Ch P-Ch
PD (t) =
R JA(t)
T J -TA
=
R JC+RCA(t)
T J-TA
= I 2 (t) x RDS(ON ) D
TJ
Typical RJA for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 130oC/W when mounted on a 0.125 in2 pad of 2oz cpper. b. 140oC/W when mounted on a 0.005 in2 pad of 2oz cpper. c. 180oC/W when mounted on a 0.0015 in2 pad of 2oz cpper.
1a
1b
1c
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%.
NDC7001C.SAM
Typical Electrical Characteristics: N-Channel
1.5
3
V GS =10V
I D , DRAIN-SOURCE CURRENT (A) 1.2
8.0 7.0
DRAIN-SOURCE ON-RESISTANCE
6.0 5.5
RDS(on) , NORMALIZED
VGS = 3.5V
2.5
4.0 4.5 5.0
5.0
0.9
2
5.5 6.0 7.0 8.0 10
4.5
0.6
1.5
4.0
0.3
1
3.5 3.0
0.5 0 0.3
0 0 1 VDS 2 3 4 , DRAIN-SOURCE VOLTAGE (V) 5
0.6 0.9 I D , DRAIN CURRENT (A)
1.2
1.5
Figure 1. N-Channel On-Region Characteristics.
Figure 2. N-Channel On-Resistance Variation with Gate Voltage and Drain Current.
2 1.8 DRAIN-SOURCE ON-RESISTANCE R DS(ON) NORMALIZED , 1.6 1.4 1.2 1 0.8 0.6 0.4 -50
2.5
V GS = 10V
R DS(on), NORMALIZED DRAIN-SOURCE ON-RESISTANCE
I D = 0.51A
V GS = 10V
2
TJ = 125C
1.5
25C
1
-55C
0.5 0 0.3 I
D
-25
0 25 50 75 100 T , JUNCTION TEMPERATURE (C) J
125
150
0.6 0.9 , DRAIN CURRENT (A)
1.2
1.5
Figure 3. N-Channel On-Resistance Variation with Temperature.
Figure 4. N-Channel On-Resistance Variation with Drain Current and Temperature.
1.5
1.2
25C 125C
V th, NORMALIZED
GATE-SOURCE THRESHOLD VOLTAGE
V DS = 10V
1.2 I D , DRAIN CURRENT (A)
T
J
= -55C
1.1
V DS = V GS I D = 250A
0.9
1
0.6
0.9
0.3
0.8
0 1 2 3 4 5 6 V GS , GATE TO SOURCE VOLTAGE (V) 7 8
0.7 -50
-25
0 25 50 75 100 TJ , JUNCTION TEMPERATURE (C)
125
150
Figure 5. N-Channel Transfer Characteristics.
Figure 6. N-Channel Gate Threshold Variation with Temperature.
NDC7001C.SAM
Typical Electrical Characteristics: N-Channel (continued)
DRAIN-SOURCE BREAKDOWN VOLTAGE
1.16
I
D
= 250A
I S , REVERSE DRAIN CURRENT (A)
1.5 1 0.5
V GS = 0V
1.12 1.08 1.04 1 0.96 0.92 0.88 -50
BV DSS , NORMALIZED
TJ = 125C
0.1
25C -55C
0.01
-25
0 25 50 75 100 TJ , JUNCTION TEMPERATURE (C)
125
150
0.001 0.2
0.4 0.6 0.8 1 V SD , BODY DIODE FORWARD VOLTAGE (V)
1.2
Figure 7. N-Channel Breakdown Voltage Variation with Temperature.
Figure 8. N-Channel Body Diode Forward Voltage Variation with Current and Temperature.
100 50
10
VDS = 25V
V GS , GATE-SOURCE VOLTAGE (V) 8
I D = 0.51A
CAPACITANCE (pF)
C iss
20 10
6
C oss C rss f = 1 MHz
4
5
2
2 1 0.1
V GS = 0 V
0.2 0.5 1 2 5 10 20 50
0 0 0.2 V DS , DRAIN TO SOURCE VOLTAGE (V) 0.4 0.6 0.8 Q g , GATE CHARGE (nC) 1 1.2
Figure 9. N-Channel Capacitance Characteristics.
Figure 10. N-Channel Gate Charge Characteristics.
0.7
V DS = 10V
0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.3 V
GS
T
J
= -55C 25C
I D , DRAIN CURRENT (A)
125C
0.6 0.9 1.2 , GATE TO SOURCE VOLTAGE (V)
1.5
Figure 11. N-Channel Transconductance Variation with Drain Current and Temperature.
NDC7001C.SAM
Typical Electrical Characteristics: P-Channel (continued)
-1
V GS = -10V
I D , DRAIN-SOURCE CURRENT (A) -0.8
3
-9.0 -8.0
-7.0
DRAIN-SOURCE ON-RESISTANCE 2.5
VGS =-4.5V -5.0
-0.6
R DS(ON) , NORMALIZED
-6.0
2
-6.0 -7.0 -8.0 -9.0 -10
-5.0
-0.4
1.5
-0.2
-4.0 -3.5
1
0.5 -0.2
0
-1 VDS
-2 -3 -4 , DRAIN-SOURCE VOLTAGE (V)
-5
-6
I
D
-0.4 -0.6 , DRAIN CURRENT (A)
-0.8
-1
Figure 12. P-Channel On-Region Characteristics.
Figure 13. P-Channel On-Resistance Variation with Gate Voltage and Drain Current.
1.8 1.6 DRAIN-SOURCE ON-RESISTANCE R DS(ON) , NORMALIZED 1.4 , NORMALIZED 1.2 1 0.8 0.6 0.4 -50
2.5
DRAIN-SOURCE ON-RESISTANCE
I D = -0.34A VG S = -10V
V GS =-10 V
2
T J = 125C
1.5
DS(on)
25C
1
R
-55C
0.5 -0.2 -0.4 -0.6 I D , DRAIN CURRENT (A) -0.8 -1
-25
0 25 50 75 100 TJ , JUNCTION TEMPERATURE (C)
125
150
Figure 14. P-Channel On-Resistance Variation with Temperature.
Figure 15. P-Channel On-Resistance Variation with Drain Current and Temperature.
-1 GATE-SOURCE THRESHOLD VOLTAGE
1.1
V DS =- 10V
-0.8 ID , DRAIN CURRENT (A)
T = -55C J 25C 125C
V th, NORMALIZED
1.05
VDS = V GS I D = -250A
1
-0.6
0.95
-0.4
0.9
-0.2
0.85
-1
-2 V
-3
GS
-4
-5
-6
-7
-8
0.8 -50
-25
, GATE TO SOURCE VOLTAGE (V)
0 25 50 75 100 TJ , JUNCTION TEMPERATURE (C)
125
150
Figure 16. P-Channel Transfer Characteristics.
Figure 17. P-Channel Gate Threshold Variation with Temperature.
NDC7001C.SAM
Typical Electrical Characteristics: P-Channel (continued)
1.15 DRAIN-SOURCE BREAKDOWN VOLTAGE
1
I D = 250A
1.1 -I S, REVERSE DRAIN CURRENT (A)
0.5
VGS =0V
BV DSS , NORMALIZED
0.1 0.05
TJ = 125C
1.05
25C -55C
1
0.01 0.005
0.95
0.9 -50
-25
0 T
J
25 50 75 100 , JUNCTION TEMPERATURE (C)
125
150
0.001 0.2
0.4
0.6 0.8 1 1.2 1.4 1.6 -V SD , BODY DIODE FORWARD VOLTAGE (V)
1.8
Figure 18. P-Channel Breakdown Voltage Variation with Temperature.
Figure 19. P-Channel Body Diode Forward Voltage Variation with Current and Temperature.
100 50
-10
I D = -0.34A
, GATE-SOURCE VOLTAGE (V)
Ciss
-8
V DS = -12V
-24 -48
CAPACITANCE (pF)
20 10
Coss
-6
5
Crss f = 1 MHz
-4
2 1 0.1
V 0 0.2 -V 0.5
DS
GS
V GS = 0 V
-2
1
2
5
10
20
50
0
0.2
0.4
, DRAIN TO SOURCE VOLTAGE (V)
0.6 0.8 1 Q g , GATE CHARGE (nC)
1.2
1.4
1.6
Figure 20. P-Channel Capacitance Characteristics.
Figure 21. P-Channel Gate Charge Characteristics.
0.5
V DS =- 10V
, TRANSCONDUCTANCE (SIEMENS) 0.4
TJ = -55C 25C
0.3
125C
0.2
0.1
g 0 -0.2 -0.4 -0.6 -0.8 -1 I D , DRAIN CURRENT (A)
Figure 22. P-Channel Transconductance Variation with Drain Current and Temperature.
FS
NDC7001C.SAM
Typical Thermal Characteristics: N & P-Channel
1.2 STEADY-STATE POWER DISSIPATION (W) I D , STEADY-STATE DRAIN CURRENT (A)
0.55
1.1
1a
0.5
1
1a
1b
0.9
1b
0.45 1c
0.8
1c
0.4
4.5"x5" FR-4 Board TA = 2 5 C Still Air VG S = 1 0 V
o
0.7
4.5"x5" FR-4 Board TA = 2 5 C Still Air
o
0.6 0 0.2 0.4 0.6 0.8 2oz COPPER MOUNTING PAD AREA (in 2 ) 1
0.35 0
0.025 0.05 0.075 0.1 2 2oz COPPER MOUNTING PAD AREA (in )
0.125
Figure 23. SOT-6 Dual Package Maximum Steady-State Power Dissipation versus Copper Mounting Pad Area.
0.4 -I D , STEADY-STATE DRAIN CURRENT (A) 3 2 1 I D , DRAIN CURRENT (A) 0.35
1a
Figure 24. N-Ch Maximum Steady-State Drain Current versus Copper Mounting Pad Area.
RD
S(O
N)
LIM
IT
10 0 1m us s
10 ms
0.5
1b
0.2 0.1
0.3
10
1c
0m
s
V
0.05
GS
= 10V
1s
0.25
SINGLE PULSE R J A = See Note 1c T A = 25C
1 2
DC
4.5"x5" FR-4 Board TA = 2 5 C Still Air VG S = - 1 0 V
o
0.02 0.01 0.125
0.2 0
0.025 0.05 0.075 0.1 2oz COPPER MOUNTING PAD AREA (in 2 )
5 10 20 V DS , DRAIN-SOURCE VOLTAGE (V)
50
70
Figure 25. P-Ch Maximum Steady-State Drain Current versus Copper Mounting Pad Area.
Figure 26. N-Channel Maximum Safe Operating Area.
3 2 1 -I D, DRAIN CURRENT (A) 0.5
S(O N) LIM IT
10 1m
10 ms
0u
s
s
RD
0.2 0.1 0.05
10
0m
s
V GS = -10V SINGLE PULSE R J A = See Note 1c T A = 25C
1 2
1s
DC
0.02 0.01
5 10 20 -V DS , DRAIN-SOURCE VOLTAGE (V)
50
70
Figure 27. P-Channel Maximum Safe Operating Area.
NDC7001C.SAM
Typical Thermal Characteristics: N & P-Channel
1
r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE
0 .5
D = 0.5
0 .2 0 .1 0.05
0.2 0.1 P(pk) 0.05 0.02 0.01
R JA (t) = r(t) * R JA R JA = See Note 1c
t1 TJ - T
t2
0.02 0.01 0 .0 0 0 1
Single Pulse
= P * R JA (t) Duty Cycle, D = t 1 / t 2
A
0 .001
0 .0 1
0 .1 t 1, TIME (sec)
1
10
100
300
Figure 28. Transient Thermal Response Curve.
Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change depending on the circuit board design.
VDD
t d(on)
ton tr
90%
to f f t d(off)
90%
tf
V IN
D
RL V OUT
DUT
VGS
VO U T
10% 10% 90%
R GEN
G
V IN
S
10%
50%
50%
PULSE WIDTH
Figure 29. N or P-Channel Switching Test Circuit.
Figure 30. N or P-Channel Switching Waveforms.
NDC7001C.SAM
SuperSOTTM-6 Tape and Reel Data and Package Dimensions
SSOT-6 Packaging Configuration: Figur e 1.0
Packaging Description:
Customize Label
Anti static Cover Tape
SSOT-6 parts are shipped in tape. The carrier tape is made from a dissipative (carbon filled) polycarbonate resin. The cover tape is a multilayer film (Heat Activated Adhesive in nature) primarily composed of polyester film, adhesive layer, sealant, and anti-static sprayed agent. These reeled parts in standard option are shipped with 3,000 units per 7" or 177cm diameter reel. The reels are dark blue in color and is made of polystyrene plastic (antistatic coated). Other option comes in 10,000 units per 13" or 330cm diameter reel. This and some other options are described in the Packaging Information table. These full reels are individually barcode labeled and placed inside a pizza box (illustrated in figure 1.0) made of recyclable corrugated brown paper with a Fairchild logo printing. One pizza box contains three reels maximum. And these pizza boxes are placed inside a barcode labeled shipping box which comes in different sizes depending on the number of parts shipped.
F63TNR Label
Embossed Carrier Tape
631 631
SSOT-6 Packaging Information Packaging Option Packaging type Qty per Reel/Tube/Bag Reel Size Box Dimension (mm) Max qty per Box Weight per unit (gm) Weight per Reel (kg) Note/Comments Standard
(no f l ow c ode )
631
631
631
Pin 1
D87Z TNR 10,000 13" 343x343x64 30,000 0.0158 0.4700
TNR 3,000 7" Dia 184x187x47 9,000 0.0158 0.1440
SSOT-6 Unit Orientation
343mm x 342mm x 64mm Intermediate box fo r D87Z Option
F63TNR Label
F63TNR Label
F63TNR Label sa mpl e 184mm x 187mm x 47mm Pizza Box fo r Standar d Opti on F63TNR Label
LOT: CBVK741B019 FSID: FDC633N QTY: 3000 SPEC:
SSOT-6 Tape Leader and Trailer Configuration: Figur e 2.0
D/C1: D9842 D/C2:
QTY1: QTY2:
SPEC REV: CPN: N/F: F
(F63TNR)3
Carrier Tape Cover Tape
Comp onent s Traile r Tape 300mm mi nimum or 75 empty poc kets Lead er Tape 500mm mi nimum or 125 emp ty poc kets
1998 Fairchild Semiconductor Corporation
August 1999, Rev. C
SuperSOTTM-6 Tape and Reel Data and Package Dimensions, continued
SSOT-6 Embossed Carrier Tape Configuration: Figure 3.0
T E1
P0
D0
F K0 Wc B0 E2 W
Tc A0 P1 D1
User Direction of Feed
Dimensions are in millimeter Pkg type SSOT-6 (8mm)
A0
3.23 +/-0.10
B0
3.18 +/-0.10
W
8.0 +/-0.3
D0
1.55 +/-0.05
D1
1.125 +/-0.125
E1
1.75 +/-0.10
E2
6.25 min
F
3.50 +/-0.05
P1
4.0 +/-0.1
P0
4.0 +/-0.1
K0
1.37 +/-0.10
T
0.255 +/-0.150
Wc
5.2 +/-0.3
Tc
0.06 +/-0.02
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481 rotational and lateral movement requirements (see sketches A, B, and C).
20 deg maximum Typical component cavity center line
0.5mm maximum
B0 20 deg maximum component rotation
0.5mm maximum
Sketch A (Side or Front Sectional View)
Component Rotation
A0 Sketch B (Top View)
Typical component center line
Sketch C (Top View)
Component lateral movement
SSOT-6 Reel Configuration: Figure 4.0
Component Rotation
W1 Measured at Hub
Dim A Max
Dim A max
Dim N
See detail AA
7" Diameter Option
B Min Dim C See detail AA W3
Dim D min
13" Diameter Option
W2 max Measured at Hub DETAIL AA
Dimensions are in inches and millimeters
Tape Size
8mm
Reel Option
7" Dia
Dim A
7.00 177.8 13.00 330
Dim B
0.059 1.5 0.059 1.5
Dim C
512 +0.020/-0.008 13 +0.5/-0.2 512 +0.020/-0.008 13 +0.5/-0.2
Dim D
0.795 20.2 0.795 20.2
Dim N
2.165 55 4.00 100
Dim W1
0.331 +0.059/-0.000 8.4 +1.5/0 0.331 +0.059/-0.000 8.4 +1.5/0
Dim W2
0.567 14.4 0.567 14.4
Dim W3 (LSL-USL)
0.311 - 0.429 7.9 - 10.9 0.311 - 0.429 7.9 - 10.9
8mm
13" Dia
July 1999, Rev. C
SuperSOTTM-6 Tape and Reel Data and Package Dimensions, continued
SuperSOT -6 (FS PKG Code 31, 33)
1:1
Scale 1:1 on letter size paper
Dimensions shown below are in: inches [millimeters]
Part Weight per unit (gram): 0.0158
1998 Fairchild Semiconductor Corporation
September 1998, Rev. A
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM CoolFETTM CROSSVOLTTM E2CMOSTM FACTTM FACT Quiet SeriesTM FAST(R) FASTrTM GTOTM HiSeCTM
DISCLAIMER
ISOPLANARTM MICROWIRETM POPTM PowerTrench QFETTM QSTM Quiet SeriesTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8
SyncFETTM TinyLogicTM UHCTM VCXTM
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. D

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